As technology develops, a system becomes more complex, the number of integrated core is also increasing, and inter-core communication is increasingly important as well. Traditional inter-core communication is usually implemented by hardware, i.e., a shared memory. As shown in FIG. 1, multiple cores are connected with a shared memory via an interconnection system. The advantage of this implementation is that the cross-transmission of information can be implemented between a plurality of cores, and its disadvantages include as follows:
1. The message passing delay is longer, because a message to be transmitted needs to be written to a shared memory first by a message creator and then the message is read by a message user from the shared memory, which require to be implemented through a system interconnection network, thereby resulting in a longer path delay, but also will compete and judge with other data accesses in order to obtain the right to use a bus; and
2. Software is required for message management, because the shared memory can only be used to store a message temporarily, the message needs to be interrupted and be notified to the message user after the message has been written to the shared memory by the message creator and the message user can be notified, and the message creator and the message user need to share, manage and maintain a message queue pointer, to avoid issues such as message coverage and message reuse.
In many practical applications, the message user is determined, the frequency and time of usage of the message are also determined. For this situation, some existing solutions use a directly connected interface for message passing, in order to improve the efficiency of message passing and reduce a passing delay, as shown in FIG. 2 and FIG. 3. FIG. 2 illustrates message passing between extendible cores via a directly connected interface, and FIG. 3 illustrates First Input First Output (FIFO) message passing based on FIG. 2. This message passing implemented by using a directly connected interface has the following defects: first, a processor must be extendible and may be expanded with a message transmitting port or a message receiving port; and second, in this approach, software is still required for message management, and software management overhead is not reduced whereas only the delay of message passing is reduced.